An alternative to CMOS VLSI called Quantum Cellular Automata (QCA) is presently being researched. Although a few basic logical circuits and devices have been examined, very little, if any, research has been done on the architecture of QCA device systems. In the context of nano communication networks, data transmission that is both dependable and efficient is still critical. The technology known as Quantum Dot Cellular Automata (QCA) has shown great promise in the development of nano-scale circuits because of its extremely low power consumption and rapid functioning. This study introduces a unique nano-communication parity-based arithmetic circuit that is reversible, error-detecting, and error-correcting. The minimal outputs are needed for the proposed structure. Based on QCA technology, the proposed nano-communication network makes use of reversible logic gates. The performance increase of the suggested parity generator and checker circuit is significant in terms of clock delay, size, and number of cells.